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vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com 6 a, microbuck ? sic414, sic424 integrated buck regulator with 5 v ldo description the vishay siliconix sic414 and sic424 are an advanced stand-alone synchronous buck regulator featuring integrated power mosfets, bootstrap switch, and an internal 5 v ldo in a space-saving powerpak mlp44-28l package. the sic414 and sic424 are capable of operating with all ceramic solutions and switching frequencies up to 1 mhz. the programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. the internal ldo may be used to supply 5 v for the gate drive circuits or it may be bypassed with an external 5 v for optimum efficiency and used to drive external n-channel mosfets or other loads. additional feat ures include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable power-save. the vishay siliconix sic414 and sic424 also provides an enable input and a power good output. features ? high efficiency > 95 % ? 6 a continuous output current capability ? integrated bootstrap switch ? integrated 5 v/200 ma ldo with bypass logic ? temperature compensated current limit ? pseudo fixed-frequency adaptive on-time control ? all ceramic solution enabled ? programmable input uvlo threshold ? independent enable pin for switcher and ldo ? selectable ultrasonic power-save mode (sic414) ? selectable power-save mode (sic424) ? internal soft-sta rt and soft-shutdown ? 1 % internal reference voltage ? power good output and over voltage protection ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? notebook, desktop, and server computers ? digital hdtv and digital consumer applications ? networking and telecommunication equipment ? printers, dsl, and stb applications ? embedded applications ? point of load power supplies typical application circuit and package option product summary input voltage range 3 v to 28 v output voltage range 0.75 v to 5.5 v operating frequency 200 khz to 1 mhz continuous output current 6 a peak efficiency 95 % package powerpak mlp44-28l pad1 a g n d p good bst v ldo v i n v out a g n d v 5 v fb pad3 lx pad2 v i n lx p g n d p g n d p g n d p g n d lx lx v i n v i n v i n v i n lx p g n d p g n d e n l to n a g n d e n /ps v lx i lim 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 20 19 1 8 17 16 15 2 8 27 26 25 24 23 22 v out v i n v out ldo_e n p good e n /ps v (tri-state) 3.3 v
www.vishay.com 2 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com pin configuration (top view) pad1 a g n d p good bst v ldo v i n v out a g n d v 5 v fb pad3 lx pad2 v i n 1 2 3 4 5 7 6 lx p g n d p g n d p g n d p g n d lx lx 15 16 17 1 8 19 20 21 v i n v i n v i n v i n lx p g n d p g n d 8 9 10 11 12 13 14 2 8 27 26 25 24 23 22 e n l to n a g n d e n /ps v lx i lim pin description pin number symbol description 1fb feedback input for switching regulator used to progra m the output voltage - connect to an external resistor divider from v out to a gnd . 2v5v bias input for internal analog circuits and gate drives - connect to external 3 v or 5 v supply or bias connection to v ldo . 3, 26, pad 1 a gnd analog ground. 4v out switcher output voltage sense pin, and also the input to the internal switch-over between v out and v ldo . 5, 8 to 11, pad 2 v in input supply voltage. 6v ldo 5 v ldo output. 7bst bootstrap pin - connect a capacitor from bst to lxbst to develop the floating supply for the high-side gate drive. 12 lxbst lx boost - connect to the bst capacitor. 15, 20, 21, pad 3 lx switching (phase) node. 13, 14, 16 to 19 p gnd power ground. 22 p good open-drain power good indicator. high impedance indicates power is good. an external pull-up resistor is required. 23 i lim current limit sense pin - used to program the cu rrent limit by connecting a resistor from i lim to lxs. 24 lxs lx sense - connect to r ilim resistor. 25 en/psv enable/power save input for the sw itching regulator - connect to a gnd to disable the switching regulator. float to operate in forced continuous mode (power save disabled). for sic414, connect to v5v to operate with ultrasonic power save mode enabled. for sic424, connect to v5v to operate with powe r save mode enabled with no minimum frequency. 27 t on on-time programming input - set the on-time by connecting through a resistor to a gnd . 28 enl enable input for the ldo - connect enl to a gnd to disable the ldo. drive with logic to + 3 v for logic control, or program the v in uvlo with a resistor divider between v in , enl, and a gnd . ordering information part number package sic414cd-t1-ge3 powerpak mlp44-28 sic424cd-t1-ge3 powerpak mlp44-28 sic414db reference board
document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 3 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com functional block diagram stresses beyond those listed under "absolute maximum ratings" may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at thes e or any other conditions beyond those indi cated in the operational sections of t he specifications is not implied. exposure to absolute ma ximum rating/conditions for extended peri ods may affect device reliability. absolute maximum ratings (t a = 25 c, unless otherwise noted) electrical parameter conditions limits unit v in to p gnd - 0.3 to + 30 v lx to p gnd - 0.3 to + 30 lx (transient < 100 ns) to p gnd - 2 to + 30 en/psv, p good , i lim to gnd - 0.3 to + (v5v + 0.3) v out , v ldo , fb to gnd - 0.3 to + (v5v + 0.3) v5v to p gnd - 0.3 to + 6 t on to p gnd - 0.3 to + (v5v - 1.5) bst to lx - 0.3 to + 6 to p gnd - 0.3 to + 35 enl - 0.3 to v in a gnd to p gnd - 0.3 to + 0.3 temperature maximum junction temperature 150 c storage temperature - 65 to 150 power dissipation junction to ambient thermal impedance (r thja ) b ic section 43 c/w maximum power dissipation ambient temperature = 25 c 3.4 w ambient temperature = 100 c 1.3 esd protection hbm 2 kv gate dri v e control on-time generator + - zero cross detector fb comparator soft start reference v 5 v 2 22 25 a g n d 3, 26, pad1 p good v 5 v control and stat u s e n /ps v 1 27 4 6 fb to n v out v alley1-limit bypass comparator a b y ldo 2 8 e n l v i n v ldo mux v 5 v dl 23 7 bst lx i lim p g n d v i n v i n v 5 v 13, 14, 16 to 19 12, 15, 20, 21, 24 pad3 5, 8 to 11, pad2
www.vishay.com 4 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com note: for proper operation, the device should be used within the recommended conditions. recommended operating range (all voltages referenced to gnd = 0 v) parameter min. typ. max. unit v in 328 v v5v to p gnd 35.5 v out to p gnd 0.75 5.5 temperature recommended ambient temperature - 40 to 85 c electrical specifications parameter symbol test conditions unless specified v in = 12 v, v5v = 5 v, t a = + 25 c for typ., - 40 c to + 85 c for min. and max., t j = < 125 c min. typ. max. unit input supplies v in uvlo threshold voltage a (not available for v5v < 4.5 v) v uvlo sensed at enl pin, rising edge 2.4 2.6 2.95 v sensed at enl pin, falling edge 2.23 2.4 2.57 v in uvlo hysteresis v uvlo_hys 0.2 v5v uvlo threshold voltage v uvlo measured at v dd pin, rising edge 2.5 2.9 3.0 measured at v dd pin, falling edge 2.4 2.7 2.9 v dd uvlo hysteresis v uvlo_hys 0.2 v in supply current i in en/psv, enl = 0 v, v in = 28 v 8.5 20 a standby mode: enl = v5v, en/psv = 0 v 130 v5v supply current i dd en/psv, enl = 0 v, v5v = 5 v 3 7 en/psv, enl = 0 v, v5v = 3 v 2 sic414, en/psv = v5v, no load, (f sw = 25 khz), v fb > 0.75 v b 1 ma sic424, en/psv = v5v, no load, v fb > 0.75 v b 0.4 v5v = 5 v, f sw = 250 khz, en/psv = floating, no load b 4 v5v = 5 v, f sw = 250 khz, en/psv = floating, no load b 2.5 controller fb comparator threshold v fb static v in and load, - 40 c to + 85 c, v5v = 3 v or 5 v 0.7425 0.750 0.7575 v frequency range b f sw continuous mode 200 1000 khz minimum f sw , (sic414 only), en/psv= v5v, no load 25 bootstrap switch resistance 10 ? timing on-time t on continuous mode operation v in = 15 v, v out = 3 v, f sw = 300 khz, r ton = 133 k ? 1350 1500 1650 ns minimum on-time b t on, min. 80 minimum off-time b t off, min. v5v = 5 v 320 v5v = 3 v 390 soft start soft start time b t ss 1.7 ms analog inputs/outputs v out input resistance r o-in 500 k ? current sense zero-crossing detector threshold voltage v sense-th lx-p gnd - 3 0 + 3 mv
document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 5 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com notes: a. v in uvlo is programmable using a resistor divider from v in to enl to a gnd . the enl voltage is compared to an internal reference. b. guaranteed by design. c. the switch-over threshold is the maximum voltage differential between the v ldo and v out pins which ensures that v ldo will internally switch-over to v out . the non-switch-over threshold is the minimum voltage differential between the v ldo and v out pins which ensures that v ldo will not switch-over to v out . d. the ldo drop out voltage is the voltage at which the ldo output drops 2 % below th e nominal regulation point. power good power good threshold voltage pg_v th_upper upper limit, v fb > internal reference 750 mv + 20 % lower limit, v fb < internal reference 750 mv - 10 start-up delay time (between pwm enable and p good high) pg_t d v5v = 5 v 4 ms v5v = 3 v 2 fault (noise-immunity) delay time b pg_i cc 5s power good leakage current pg_i lk 1a power good on-resistance pg_r ds-on 10 ? fault protection valley current limit v5v = 5 v, r ilim = 5 k ? 345a i lim source current i lim 8a i lim comparator offset voltage v ilm-lk with respect to a gnd - 8 0 + 8 mv output under-voltage fault v ouv_fault v fb with respect to internal 750 mv reference, 8 consecutive clocks - 25 % smart power-save protection threshold voltage b p save_vth v fb with respect to internal 750 mv reference + 10 over-voltage protection threshold v fb with respect to internal 750 mv reference + 20 over-voltage fault delay b t ov-delay 5s over temperature shutdown b t shut 10 c hysteresis 150 c logic inputs/outputs logic input high voltage v ih enl 1 v logic input low voltage v il 0.4 en/psv input for psave operation b % of v5v 45 100 % en/psv input for forced continuous operation b 1v 42 en/psv input for disabling switcher 00.4v en/psv input bias current i en en/psv = v5v or a gnd - 10 + 10 a enl input bias current v in = 28 v 11 18 fb input bias current fbl_i lk fb = v5v or a gnd - 1 + 1 linear dropout regulator v ldo accuracy v ldo_acc v ldo load = 10 ma 4.9 5 5.1 v ldo current limit ldo_i lim start-up and foldback, v in = 12 v 115 ma operating current limit, v in = 12 v 135 200 v ldo to v out switch-over threshold c v ldo-bps - 140 + 140 mv v ldo to v out non-switch-over threshold c v ldo-nbps - 450 + 450 v ldo to v out switch-over resistance r ldo v out = 5 v 2 ? ldo drop out voltage d from v in to v vldo , v vldo = 5 v, i vldo = 100 ma 1.2 v electrical specifications parameter symbol test conditions unless specified v in = 12 v, v5v = 5 v, t a = + 25 c for typ., - 40 c to + 85 c for min. and max., t j = < 125 c min. typ. max. unit
www.vishay.com 6 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com electrical characteristics efficiency vs. i out (in continuous conduction mode) v out vs. i out (in continuous conduction mode) v out vs. v in at i out = 0 a (in continuous conduction mode, fsw = 500 khz) 0 10 20 30 40 50 60 70 80 90 01234567 efficiency (%) i out (a) v in = 12 v, v out = 1 v, fsw = 500 khz v out (v) i out (a) 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 01234567 v in = 12 v, v out = 1 v, fsw = 500 khz v out (v) v in (v) 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 3691215182124 v out = 1 v, i out = 0 a efficiency vs. i out (in power-save-mode) v out vs. i out (in power-save-mode) v out vs. v in at i out = 6 a (in continuous conduction mode, fsw = 500 khz) efficiency (%) i out (a) 30 40 50 60 70 80 90 01234567 v in = 12 v, v out = 1 v, fsw = 500 khz (at 6 a) v out (v) i out (a) 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 01234567 v in = 12 v, v out = 1 v, fsw = 500 khz (at 6 a) v out (v) v in (v) 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 3691215182124 v out = 1 v, i out = 6 a
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 7 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com electrical characteristics v out vs. v in (i out = 0 a in power-save-mode) v out ripple vs. v in (i out = 0 a in continuous conduction mode) fsw vs. i out (in continuous conduction mode) v out (v) v in (v) 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 3691215182124 v out = 1 v, i out = 0 a v out ripple (mv) v in (v) 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 v out = 1 v, i out = 0 a, fsw = 500 khz fsw (khz) i out (a) 350 375 400 425 450 475 500 525 550 01234567 v in = 12 v, v out = 1 v, fsw = 500 khz (at 6 a) v out ripple vs. v in (i out = 6 a in continuous conduction mode) v out ripple vs. v in (i out = 0 a in power-save-mode) fsw vs. i out (in power-save-mode) v out ripple (mv) v in (v) 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 v out = 1 v, i out = 6 a, fsw = 500 khz v out ripple (mv) v in (v) 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 v out = 1 v, i out = 0 a, psv mode fsw (khz) i out (a) 20 70 120 170 220 270 320 370 420 470 520 01234567 v in = 12 v, v out = 1 v, fsw = 500 khz (at 6 a)
www.vishay.com 8 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com electrical characteristics v out ripple in continuous conduction mode (no load) (v in = 12 v, v out = 1 v, fsw = 500 khz) transient response in continuous conduction mode (0.2 a - 6 a) (v in = 12 v, v out = 1 v, fsw = 500 khz) transient response in power save mode (0.2 a - 6 a) (v in = 12 v, v out = 1 v, fsw = 500 khz at 6a) o u tp u tc u rrent 2 a/di v . 5 s/di v . o u tp u t v oltage 50 m v /di v . 5 s/di v . ac co u pling o u tp u tc u rrent 2 a/di v . 5 s/di v . o u tp u t v oltage 50 m v /di v . 5 s/di v . ac co u pling v out ripple in power save mode (no load) (v in = 12 v, v out = 1 v) transient response in continuous conduction mode (6 a - 0.2 a) (v in = 12 v, v out = 1 v, fsw = 500 khz) transient response in power save mode (6 a - 0.2 a) (v in = 12 v, v out = 1 v, fsw = 500 khz at 6 a) lx switching node 2v/div. 2ms/div output ripple voltage 20 mv/div. 2 ms/div o u tp u tc u rrent 2 a/di v . 5 s/di v . o u tp u t v oltage 50 m v /di v . 5 s/di v . ac co u pling o u tp u tc u rrent 2 a/di v . 5 s/di v . o u tp u t v oltage 50 m v /di v . 5 s/di v . ac co u pling
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 9 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com electrical characteristics applications information device overview the sic414 and sic424 are a step down synchronous buck dc/dc converter with integrated power fets and programmable ldo. the device is capable of 6 a operation at very high efficiency in a tiny 4 mm x 4 mm - 28 pin package. the programmable operating frequency range of 200 khz to 1 mhz, enables the user to optimize the solution for minimum board space and optimum efficiency. the buck controller employs pseudo-fixed frequency adaptive on-time control. this control scheme allows fast transient response thereby lowering the size of the power components used in the system. the buck controller employs pseudo-fixed frequency adaptive on-time control. this control scheme allows fast transient response thereby lowering the size of the power components used in the system. input voltage range the sic414 and sic424 requires two input supplies for normal operation: v in and v5v. v in operates over the wide range from 3 v to 28 v. v5v requires a 3.3 v or 5 v supply input that can be an external source or the internal ldo configured to supply 5 v. pseudo-fixed frequency ad aptive on-time control the pwm control method used by the sic414 and sic424 is pseudo-fixed frequency, adaptive on-time, as shown in figure 1. the ripple voltage gener ated at the output capacitor esr is used as a pwm ramp signal. this ripple is used to trigger the on-time of the controller. the adaptive on-time is determined by an internal one-shot timer. when the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the high side mosfet. the pulse period is determined by v out and v in ; the period is proportional to output voltage and inversely proportional to input voltage. with this adaptive on-time arrangement, the device automatically anticipates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the adaptive on-time control ha s significant advantages over traditional control methods used in the controllers today. ? reduced component count by eliminating dcr sense or current sense resistor as no need of a sensing inductor current. ? reduced saves external components used for compensation by eliminating the no error amplifier and other components. ? ultra fast transient response because of fast loop, absence of error amplifier speeds up the transient response. ? predictable frequency spread because of constant on-time architecture. ? fast transient response enables operation with minimum output capacitance overall, superior performance compared to fixed fr equency architectures. overall, superior performance compared to fixed frequency architectures. start-up with v in ramping up (v in = 12 v, v out = 1 v, fsw = 500 khz) over-current protection (v in = 12 v, v out = 1 v, fsw = 500 khz) figure 1 - pwm control method, v out ripple v i n c i n v lx q1 q2 l esr + fb v lx t o n v fb c out v out fb threshold
www.vishay.com 10 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com on-time one-shot generator (t on ) and operating frequency the figure 2 shows the on-chip implementation of on-time generation. the fb comparat or output goes high when v fb is less than the internal 750 mv reference. this feeds into the gate drive and turns on the high-side mosfet, and also starts the one-shot timer. the one-shot timer uses an internal comparator and a capacitor . one comparator input is connected to v out , the other input is connected to the capacitor. when the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turns off. this method automatically pr oduces an on-time that is proportional to v out and inversely proportional to v in . under steady-state conditions, th e switching frequency can be determined from the on-time by the following equation. the sic414 and sic424 uses an external resistor to set the ontime which indirectly sets the frequency. the on-time can be programmed to provide operating frequency from 200 khz to 1 mhz using a resistor between the t on pin and ground. the resistor value is selected by the following equation. the maximum r ton value allowed is shown by the following equation. immediately after the on-time, the dl (drive signal for the low side fet) output drives high to turn on the low-side mosfet. dl has a minimum high time of ~ 320 ns, after which dl continues to stay high until one of the following occurs: ?v fb falls below the 750 mv reference. ? the zero cross detector senses that the voltage on the lx node is below ground. power save is activated when a zero crossing is detected. t on limitations and v5 v supply voltage for v5v below 4.5 v, the t on accuracy may be limited by the input voltage. the original r ton equation is accurate if v in satisfies the below relation over the entire v in range: v in < (v5v - 1.6 v) x 10 if v in exceeds (v5v - 1.6 v) x 10, for all or part of the v in range, the r ton equation is not accurate. in all cases where v in > (v5v - 1.6 v ) x 10, the r ton equation must be modified as follows. note that when v in > (v5v - 1.6 v) x 10, the actual on-time is fixed and does not vary with v in . when operating in this condition, the switching frequency will vary inversely with v in rather than approximating a fixed frequency. v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 750 mv reference voltage, see figure 3. note that this control method regulates the valley of the output ripple voltage, not the dc value. the dc output voltage v out is offset by the output ripple according to the following equation. v out = 0.75 x (1 + r 1 /r 2 ) + v ripple /2 enable and power-save inputs the en/psv and enl inputs are used to enable or disable the switching regulator and th e ldo. when en/psv is low (grounded), the switching regulator is off and in its lowest power state. when off, the output of the switching regulator soft-discharges the output into a 10 ? internal resistor via the v out pin. when en/psv is allowed to float, the pin voltage will float to 33 % of the voltage at v5v. the switching regulator turns on with power-save disabled and all switching is in forced continuous mode. for v5v < 4.5 v, it is recommended to force 33 % of the v5v voltage on the en/psv pin to operate in forced continuous mode. when en/psv is high (above 45 % of the voltag e at v5v) for sic414, the switching regulator turns on with ultrasonic figure 2 - on-time generation fb v ref - + v out v i n r ton on-time = k x r ton x ( v out/ v i n ) fb comparator one-shot timer gate dri v es dh dl q1 q2 l q1 esr fb v out c out v lx + v in f s w = v out t o n x v i n r ton = 1 25 pf x f sw - 400 x v in v out r ton_max = v i n _mi n 15 a figure 3 - output voltage selection r ton = 1 25 pf x f sw - 400 x (v5v - 1.6 v) x 10 v out v out r 1 r 2 to fb pin
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com power-save enabled. the sic414 ultrasonic power-save operation maintains a minimum switching frequency of 25 khz, for applications with stringent audio requirements. when en/psv is high (above 45 % of the voltage at v5v) for sic424, the switching regulator turns on with power-save enabled. the sic424 power-save operation is designed to maximize efficiency at light loads with no minimum frequency limits. this makes the sic424 an excellent choice for portable and battery-operated systems. the enl input is used to control the internal ldo. this input provides a second function by acting as a v in ulvo sensor for the switching regulator. when enl is low (grounded), the ldo is off. when enl is a logic high but below the v in uvlo threshold (2.6 v typical), then the ldo is on and the switcher is off. when enl is above the v in uvlo threshold, the ldo is enabled and the switcher is also enabled if the en/psv pin is not grounded. forced continuous mode operation the sic414 and sic424 operat es the switcher in forced continuous mode (fcm) by floating the en/psv pin (see figure 4). in this mode of operation, the mosfets are turned on alternately to each other with a short dead time between them to avoid cross conducti on. this feature results in uniform frequency across the full load range with the trade-off being poor efficiency at light loads due to the high-frequency switching of the mosfets. for v5v < 4.5 v, it is recommended to force 33 % of the v5v voltage on the en/psv pin to operate in forced continuous mode. ultrasonic power-sa ve operation (sic414) the sic414 provides ultrasonic power-save operation at light loads, with the minimum operating frequency fixed at slightly under 25 khz. this is accomplished by using an internal timer that monitors the time between consecutive high-side gate pulses. if the time exceeds 40 s, dl drives high to turn the low-side mosfet on. this draws current from v out through the inductor, forcing both v out and v fb to fall. when v fb drops to the 750 mv threshold, the next dh (the drive signal for the high side fet) on-time is triggered. after the on-time is comple ted the high-side mosfet is turned off and the low-side mosfet turns on. the low-side mosfet remains on until the inductor current ramps down to zero, at which point the lo w-side mosfet is turned off. because the on-times are forced to occur at intervals no greater than 40 s, the frequency will not fall far below 25 khz. figure 5 shows ultrasonic power-save operation. power-save mode operation (sic424) the sic424 provides power-save operation at light loads with no minimum operating frequency. with power-save enabled, the internal zero crossing comparator monitors the inductor current via the voltage across the low-side mosfet during the off-time. if the inductor current falls to zero for 8 consecutive switching cycles, the controller enters power-save operation. it will turn off the low-side mosfet on each subsequent cycle provided that the current crosses zero. at this time both mosfets remain off until v fb drops to the 750 mv threshold. because the mosfets are off , the load is supplied by the output capacitor. if the inductor current does not reach zero on any switching cycle, the controller immediately exits powersave and returns to forced continuous mode. figure 6 shows power-save mode operation at light loads. figure 4 - forced continuous mode operation fb ripple v oltage ( v fb ) ind u ctor c u rrent dc load c u rrent fb threshold (750 m v ) dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold dl dri v es high w hen on-time is completed. dl remains high u ntil v fb falls to the fb threshold. figure 5 - ultrasonic power-save operation after the 40 s time - out, dl drives high if v fb has not reached the fb threshold
www.vishay.com 12 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com smart power-save protection active loads may leak current from a higher voltage into the switcher output. under light lo ad conditions with power-save mode enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shutd-own. smart power-save prevents this condition. when the fb voltage exceeds 10 % above nominal, the device immediately disables power-save, and dl drives high to turn on the low-side mo sfet. this draws current from v out through the inductor and causes v out to fall. when v fb drops back to the 750 mv trip point, a normal t on switching cycle begins. this method prevents a hard ovp shutdown and also cycles energy from v out back to v in . it also minimizes operating power by avoiding forced conduction mode operation. figure 7 shows typical waveforms for the smart power-save feature. smartdrive tm for each dh pulse the dh driver initially turns on the high side mosfet at a lower speed, allowing a softer, smooth turn-off of the low-side diode. once the diode is off and the lx voltage has risen 0.5 v above p gnd , the smartdrive circuit automatically drives th e high-side mosfet on at a rapid rate. this technique reduces switchi ng losses while maintaining high efficiency and also avoids the need for snubbers for the power mosfets. current limit protection the device features programmable current limiting, which is accomplished by using the r ds(on) of the lower mosfet for current sensing. the current lim it is set by rilim resistor. the r ilim resistor connects from the ilim pin to the lxs pin which is also the drain of the low-side mosfet. when the low-side mosfet is on, an internal ~ 8 a current flows from the ilim pin and through the r ilim resistor, creating a voltage drop across the resistor. whil e the low-side mosfet is on, the inductor current flows through it and creates a voltage across the r ds(on) . the voltage across the mosfet is neg- ative with respect to ground. if this mosfet voltage drop exceeds the voltage across r ilim , the voltage at the ilim pin will be negative and current limit will activate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to brin g the ilim voltage back up to zero. this method regulates the inductor valley current at the level shown by ilim in figure 8. setting the valley current limit to 6 a results in a 6 a peak inductor current plus peak ripple current. in this situation, the average (load) current through the inductor is 6 a plus one-half the peak-to-peak ripple current. the internal 8 a current source is temperature compensated at 4100 ppm in order to provide tracking with the r ds(on) . the r ilim value is calculated by the following equation. r ilim = 1250 x i lim x [0.088 x (5 v - v5v) + 1] when selecting a value for r ilim do not exceed the absolute maximum voltage value for the ilim pin. note that because the low-side mosfet with low r ds(on) is used for current sensing, the pcb layout, solder connections, and pcb connection to the lx node must be done carefully to obtain good results. r ilim should be connected directly to lxs (pin 24). figure 6 - power-save mode operation figure 7 - smart power-save dead time varies according to load fb threshold (750 mv) fb ripple voltage (v fb ) inductor current zero (0 a) on-time (t on ) dh on-time is triggered when v fb reaches the fb threshold dl drives high when on-time is completed. dl remains high until inductor current reaches zero. dh dl v out drifts u p to d u e to leakage c u rrent flo w ing into c out smart po w er sa v e threshold ( 8 25 m v ) fb threshold dh and dl off high-side dri v e (dh) lo w -side dri v e (dl) n ormal v out ripple v out discharges v ia ind u ctor and lo w -side mosfet single dh on-time p u lse after dl t u rn-off n ormal dl p u lse after dh on-time p u lse dl t u rns on w hen smart psa v e threshold is reached dl t u rns off fb threshold is reached figure 8 - valley current limit i peak i load i lim time ind u ctor c u rrent
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com soft-start of pwm regulator soft-start is achieved in the pwm regulator by using an internal voltage ramp as the reference for the fb comparator. the voltage ramp is generated using an internal charge pump which drives the reference from zero to 750 mv in ~ 1.8 mv increments, using an internal ~ 500 khz oscillator. when the ramp voltage reaches 750 mv, the ramp is ignored and the fb comparator switches over to a fixed 750 mv threshold. during soft- start the output voltage tracks the internal ramp, which limits the start-up inrush current and provides a controlled soft-sta rt profile for a wide range of applications. typical soft-start ramp time is 1.7 ms. during soft-start the regulator turns off the low-side mosfet on any cycle if the inductor current falls to zero. this prevents negative inductor current, allowing the device to start into a pre-biased output. this soft start operation is implemented even if fcm is selected. fcm operation is allowed only after p good is high. power good output the power good (p good ) output is an open-drain output which requires a pull-up resistor. when the output voltage is 10 % below the nominal voltage, p good is pulled low. it is held low until the output vo ltage returns to the nominal voltage. p good is held low during start-up and will not be allowed to transition high until soft-start is completed (when v fb reaches 750 mv) and typically 4 ms has passed. p good will transition low if the v fb pin exceeds + 20 % of nominal, which is also the over-voltage shutdown threshold (900 mv). p good also pulls low if the en/psv pin is low when v5v is present. output over-vol tage protection over-voltage protection (ovp) becomes active as soon as the device is enabled. the threshold is set at 750 mv + 20 % (900 mv). when v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the controll er remains off, until the en/psv input is toggled or v5v is cycl ed. there is a 5 s delay built into the ovp detector to prevent false transitions. p good is also low after an ovp event. output under-voltage protection when v fb falls to 75 % of its nominal voltage (falls to 562.5 mv) for eight consecutive clock cycles, the switcher is shut off and the dh and dl drives are pulled low to turn off the mosfets. the controller stays off until en/psv is toggled or v5v is cycled. v5v uvlo, and por under-voltage lock-out (uvlo) circuitry inhibits switching and tri-states the dh/dl driver s until v5v rises above 2.9 v. an internal power-on reset (por) occurs when v5v exceeds 2.9 v, which resets the fault latch and soft-start counter to begin the soft-start cycle. the sic414 and sic424 then begins a soft-start cycle . the pwm will shut off if v5v falls below 2.7 v. ldo regulator the device features an integrated ldo regulator with a fixed output voltage of 5 v. there is also an enable pin (enl) for the ldo that provides independe nt control. the ldo voltage can also be used to provide the bias voltage for the switching regulator. a minimum capacitance of 1 f referenced to a gnd is normally required at the output of the ldo for stability. if the ldo is providing bias power to the device, then a minimum 0.1 f capacitor referenced to a gnd is required, along with a minimum 1 f capacitor referenced to p gnd to filter the gate drive pulses. refer to the layout guide-lines section. ldo start-up before start-up, the ldo checks the status of the following signals to ensure proper operation can be maintained. 1. enl pin 2. v ldo output 3. v in input voltage when the enl pin is high, the ldo will begin start-up, see figure 9. during the initia l phase, when the ldo output voltage is near zero, the ldo initiates a current-limited start-up (typically 85 ma) to charge the output capacitor. when v ldo has reached 90 % of the final value, the ldo current limit is increased to ~ 200 ma and the ldo output is quickly driven to the nominal value by the internal ldo reg- ulator. ldo switch-over function the sic414 and sic424 includes a switch-over function for the ldo. the switch-over function is designed to increase efficiency by using the more efficient dc/dc converter to power the ldo output, avoiding the less efficient ldo regulator when possible. the switch-over function connects the v ldo pin directly to the v out pin using an internal switch. when the switch-over is complete the ldo is turned off, which results in a power saving s and maximizes efficiency. if the ldo output is used to bi as the sic414 and sic424, then after switch-over the device is self-powered from the switching regulator with the ldo turned off. the switch-over logic waits for 32 switching cycles before it starts the switch-over. there are two methods that determine the switch-over of v ldo to v out . in the first method, the ldo is already in regulation and the dc/dc converter is later enabled. as soon as the p good output goes high, the 32 cycle counter is started. the voltages at the v ldo and v out pins are then compared; if the figure 9 - ldo start-up constant c u rrent start u p v v ldo final 90 % of v v ldo final v oltage reg u lating w ith ~ 200 ma c u rrent limit
www.vishay.com 14 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com two voltages are within 300 mv (typically) of each other, within 32 cycles, the v ldo pin connects to the v out pin using an internal switch, and the ldo is turned off. in the second method, the dc/dc converter is already running and the ldo is enabled. in th is case the 32 cycles are started as soon as the ldo reaches 90 % of its final value. at this time, the v ldo and v out pins are compared, and if within 300 mv (typical ly) the switch-over occurs and the ldo is turned off. switch-over limitations on v out and v ldo because the internal switch-over circuit always compares the v out and v ldo pins at start-up, there are voltage limitations on permissible combinations of these pins. consider the situation where v out is programmed to 4.7 v. after start-up, the device would connect v out to v ldo and disable the ldo, since the two voltages are within the 300 mv switch-over window. to avoid unwanted switch- over, the minimum difference between the voltages for v out and v ldo should be 500 mv. switch-over mosfet parasitic diodes the switch-over mosfet contai ns parasitic diodes that are inherent to its construction, as shown in figure 10. there are some important design rules that must be followed to prevent forward bias of these diodes. the following two conditions need to be satisfied in order for the parasitic diodes to stay off. ? v5v ? v ldo ? v5v ? v out if either v ldo or v out is higher than v5v, then the respective diode will turn on and the sic414 and sic424 operating current will flow through this diode. this has the potential of damaging the device. enl pin and v in uvlo the enl pin also acts as the switcher under-voltage lockout for the v in supply. the v in uvlo voltage is programmable via a resistor divider at the v in , enl, and a gnd pins. enl is the enable/disable signal for the ldo. in order to implement the v in uvlo there is also a ti ming requirement that needs to be satisfied. if the enl pin transitions low within 2 switching cycles and is < 1 v, then the ldo will turn off, but the switcher remains on. if enl goes below the v in uvlo threshold and stays above 1 v, then the switcher will turn off but the ldo remains on. the v in uvlo function has a typical threshold of 2.6 v on the v in rising edge.the falling edge threshold is 2.4 v. note that it is possible to o perate the switcher with the ldo disabled, but the enl pin must be below the logic low threshold (0.4 v maximum). t he table below summarizes the function of the enl and en pins, with respect to the rising edge of enl. figure 11 below shows the enl voltage thresholds and their effect on ldo and switcher operation. enl logic control of pwm operation when the enl input is driven abov e 2.6 v, it is impossible to determine if the ldo output is going to be used to power the device or not. in self-powered operation where the ldo will power the device, it is necessary during the ldo start-up to hold the pwm switching off until the ldo has reached 90 % of the final value. this prevents overloading the current- limited ldo output during the ldo start-up. however, if the switcher was previously o perating (with en/psv high but enl at ground, and v5v supplied externally), then it is undesirable to shut down the switcher. to prevent this, when the enl input is above 2.6 v (above the v in uvlo threshold), the internal logic checks the p good signal. if p good is high, then the switcher is already running and the ldo will run through the start-up cycle without affecting the switcher. if p good is low, then the ldo will not allow any pwm switching until the ldo output has reached 90 % of its final value. figure 10 - switch-over mosfet parasitic diodes v out v ldo v 5 v parastic diode parastic diode s w itcho v er mosfet s w itcho v er control en enl ldo switcher low low, < 0.4 v off off high low, < 0.4 v off on low high, < 2.6 v on off high high, < 2.6 v on off low high, > 2.6 v on off high high, > 2.6 v on on figure 11 - enl thresholds
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 15 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com using the on-chip ldo to bias the sic414/sic424 the following steps must be followed when using the onchip ldo to bias the device. ? connect v5v to v ldo before enabling the ldo. ? any external load on v ldo should not exceed 40 ma until the ldo voltage has reached 90 % of final value. ? do not connect the en pin directly to the v5v or any other supply voltage if v out is greater than or equal to 4.5 v. many applications connect the en pin to v5v and control the on/off of the ldo and pwm simultaneously with the enl pin. this allows one signal to control both the bias and power output of the sic414 and sic424. when v out > 4.5 v this configuration can cause problem s due to the parasitic diodes in the ldo switchover circuitry. after the v out > 4.5 v pwm output is up and running the switchover diodes can hold up v5v > uvlo even if the enl pin is grounded, turning off the ldo. operating in this way can potentially damage the part. design procedure when designing a switch mode power supply, the input voltage range, load current, switching frequency, and inductor ripple current must be specified. the maximum input voltage (v inmax ) is the highest specified input voltage. the minimum input voltage (v inmin ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters define the design: ? nominal output voltage (v out ) ? static or dc output tolerance ? transient response ? maximum load current (i out ) there are two values of load cu rrent to evaluate - continuous load current and peak load current. continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design: ? v in = 12 v 10 % ? v out = 1.5 v 4 % ? f sw = 250 khz ? load = 6 a maximum frequency selection selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. the desired switching frequency is 250 khz which results from using component selected for optimum size and cost. a resistor (r ton ) is used to program the on-time (indirectly setting the frequency) using the following equation. to select r ton , use the maximum value for v in , and for t on use the value associated with maximum v in . t on = 303 ns at 13.2 v in , 1 v out , 250 khz substituting for r ton results in the following solution r ton = 130.9 k ? , use r ton = 130 k ? . inductor selection in order to determine the indu ctance, the ripple current must first be defined. low inductor values result in smaller size but create higher ripple current which can reduce efficiency. higher inductor values will reduce the ripple current/voltage and for a given dc resistance are more efficient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efficiency are all used in the selection process. the ripple current will also set the boundary for power-save operation. the switching w ill typically enter power-save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 4 a then power-save operation will typically start for loads less than 2 a. if ripple current is set at 40 % of maximum load current, then power- save will start for loads less than 20 % of maximum current. the inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. this provides an optim al trade-off between cost, efficiency, and transient performance. during the dh on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown next. example in this example, the inductor ripple current is set equal to 50 % of the maximum load current. therefore ripple current will be 50 % x 6 a or 3 a. to find the minimum inductance needed, use the v in and t on values that correspond to v inmax. a slightly larger value of 1.5 h is selected. this will decrease the maximum i ripple to 2.53 a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the ripple current under minimum v in conditions is also checked using the following equations. r ton = 1 25 pf x f sw - 400 x v in v out t o n = v out v i n max. x f s w l = ( v i n - v out ) x t o n i ripple l = (13.2 v - 1 v ) x 31 8 ns 3 a = 1.26 h
www.vishay.com 16 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com capacitor selection the output capacitors are chosen based on required esr and capacitance. the maximum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal is for the output voltage regulation to be 4 % under static conditions. the internal 750 mv reference tolerance is 1 %. assuming a 1 % tolerance from the fb resistor divider, this allows 2 % tolerance due to v out ripple. since this 2 % error comes from 1/2 of the ripple voltage, the allowable ripple is 4 %, or 40 mv for a 1 v output. the maximum ripple current of 2.53 a creates a ripple voltage across the esr. the maximum esr value allowed is shown by the following equations. the output capacitance is chosen to meet transient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the requ ired capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1 s), the output capacitor must absorb all the inductor's stored energy. this will cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.150 (100 mv rise upon load release), and a 6 a load release, the required capacitance is shown by the next equation. if the load release is relatively slow, the output capacitance can be reduced. at heavy loads during normal switching, when the fb pin is above the 750 mv reference, the dl output is high and the low-si de mosfet is on. during this time, the voltage across the inductor is approximately - v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the - di/dt in the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. the following can be used to calculate the needed capacitance for a given di load /dt: peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 10 + 1/2 x 2.53 = 7.26 a rate of change of load current = di load /dt i max = maximum load release = 6 a example this causes the output current to move from 6 a to 0 a in 4.8 s, giving the minimum ou tput capacitance requirement shown in the following equation. note that c out is much smaller in this example, 443 f compared to 772 f based on a worst-case load release. to meet the two design criteria of minimum 443 f and maximum 15 m ? esr, select two capa citors rated at 220 f and 15 m ? esr or less. it is recommended that an additional small capacitor be placed in parallel with c out in order to filter high frequency switching noise. stability considerations unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely after the minimum off-time has expired. in extreme cases the noise can cause three or more successive on-ti mes. double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. th is form of instability can usually be avoided by providing the fb pin with a smooth, clean ripple signal that is at least 10 mv p-p , which may dictate the need to increase the esr of t he output capacitors. it is also imperative to provide a prope r pcb layout as discussed in the layout guidelines section. t o n _ v i n mi n = 25 pf x r to n x v out v i n mi n i ripple = ( v i n - v out ) x t o n l i ripple_ v i n mi n = (10. 8 - 1 v ) x 311 ns 1.5 h = 2.03 a + 10 ns = 311 ns esr max = v ripple i ripplemax esr max = 15. 8 m = 40 m v 2.53 a c out_mi n = l (i out + x i ripplemax ) 2 ( v peak ) 2 - ( v out ) 2 1 2 c out_mi n = 1.5 h (6 a + x 2.53) 2 (1.05) 2 - (1 v ) 2 c out_mi n = 772 f 1 2 c out = i lpk x l x - x dt 2 ( v pk - v out ) i lpk v out i max dl load load dl load dt = 1.25 a 1 s c out = 7.26 x 1.5 h x - x 1 s 2 (1.05 v - 1 v ) 7.26 1 v 6 a 1.25 a c out = 443 f
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 17 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com another way to eliminate doubling-pulsing is to add a small (~ 10 pf) capacitor across the upper feedback resistor, as shown in figure 12. this capacit or should be left unpopulated unless it can be confirmed that double-pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional connection on the pcb should be available for this capacitor. esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple env elope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. one simple way to solve this problem is to add trace resistance in the high current output path. a side effect of adding trace resistance is a decrease in load regulation. esr requirements a minimum esr is required for two reasons. one reason is to generate enough output ripple voltage to provide 10 mv p-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insufficient esr. the on-time control regulates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging and discharging during the switching cycle. for most applications, the total output ripple voltage is domi nated by the output capacitors, typically sp or poscap devices . for stability the esr zero of the output capacitor should be lower than approximately one-third the switching frequency. the formula for minimum esr is shown by the following equation. using ceramic output capacitors when applications use ceramic output capacitors, the esr is normally too small to meet the previously stated esr criteria. in these applications it is necessary to add a small virtual esr network composed of two capacitors and one resistor, as shown in figure 12. this network creates a ramp voltage across cl, analogous to the ramp voltage generated across the esr of a standard capa citor. this ramp is then capacitive coupled into the fb pin via capacitor c c . dropout performance the output voltage adjustment range for continuous conduction operation is limited by the fixed 250 ns (typical) minimum off-time of the one-shot. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the duty-factor limitation is shown by the next equation. the inductor resistance and mo sfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy (v out controller) three factors affect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator off set is trimmed so that under static conditions it trips when the feedback pin is 750 mv, 1 %. the on-time pulse from the sic414 and sic424 in the design example is calculated to give a pseudo-fixed frequency of 250 khz. some frequency variation with line and load is expected. this variation changes the output ripple voltage. because constant on-time converters regulate to the valley of the output ripple, 1/2 of the output ripple appears as a dc regulation error. for example, if the output ripple is 50 mv with v in = 6 v, then the measured dc output will be 25 mv above the comparator trip point. if the ripple increases to 80 mv with v in = 25 v, then the measured dc output will be 40 mv above the comparator trip. the best way to minimize this effect is to minimize the output ripple. to compensate for valley regulat ion, it may be desirable to use passive droop. take the feedback directly from the output side of the inductor an d place a small amount of trace resistance between the inductor and output capacitor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive figure 12 - capacitor coupling to fb pin v out r 1 r 2 to fb pin c top esr mi n = 3 2 x x c out x f s w figure 13 - virtual esr ramp circuit duty = t o n (mi n ) t o n (mi n ) x t off(max)
www.vishay.com 18 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. the use of 1 % feedback resistors may result in up to an additional 1 % error. if tighter dc accuracy is required, resistors with lower tolerances should be used. the output inductor value may change with current. this will change the output ripple and therefore will have a minor effect on the dc output voltage. the output esr also affects the output ripple and thus has a minor effect on the dc output voltage. switching freque ncy variations the switching frequency will vary depending on line and load conditions. the line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external mosfet switching. as v in increases, these factors make the actual dh on-time slightly longer than the ideal on-time. the net effect is that frequency tends to falls slightly with increasing input voltage inductor. an adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from v in as losses increase). the on-time is essentially constant for a given v out /v in combination, to offset the losses the off-time will tend to reduce slightly as load increases. the net effect is that switching frequency increases slightly with increasing load. bill of materials qty. ref. designator description value voltage footprint part number manufacturer 1u1 sic424 cot buck converter mlpq-28 4 x 4 mm sic424 vishay 4 c16, c18, c17, c23 220 f, 10 v d 220 f 10 v sm593d 593d227x0010e2te3 vishay 4 c15, c20, c21, c22 10 f, 16 v, x7r.b, 1206 10 f 16 v sm1206 grm31cr71c106kac7l murata 1 l1 1 h 1 h ihlp2525 ihlp2525ezer1r0m01 vishay 1 q1 si4812bdy-e3 so-8 si4812bdy vishay 5 c1, c2, c3, c4, c29 cap. 22 f, 16 v, 1210 22 f 16 v sm1210 grm32er71c226me18l murata 3 c8, c9, c10 cap. 10 f, 25 v, 1210 10 f 25 v sm1210 tmk325b7106mm-t taiyo yuden 1 c26 4.7 f, 10 v, 0805 4.7 f 10 v sm0805 LMK212B7475KG-T taiyo yuden 1 c12 cap. radial 150 f, 35 v 150 f 35 v radial eu-fm1v151 panasonic 1r4 1 ? , 2512 1 ? 200 v sm2512 crcw25121r00fkeg vishay 2 r7, r11 res. 0 ? 0 ? 50 v sm0603 crcw0603 0000zoea vishay 1 r39 0r, 50 v, 0402 0 ? 50 v sm0402 crcw04020000zoed vishay 1 r3 res. 1k, 50 v, 0402 1k 50 v sm0402 crcw04021k00fked vishay 2 r5, r6 res. 100k, 0603 100k 50 v sm0603 crcw0603 100k fkea vishay 3 r8, r10, r15 res. 10k, 50 v, 0603 10k 50 v sm0603 crcw060310kfked vishay 1c6 cap. cer 1 f, 35 v, x7r 0805 1 f 35 v sm0805 gmk212b7105kg-t murata 1r23 res. 16.5 k ?? 1/10 w, 1%, 0603 smd 16.5k 50 v sm0603 crcw060316k5fkea vishay 1 r13 res. 1k, 50 v, 0402 1k 50 v sm0402 crcw04021k00fked vishay 1 c30 cap. 180 pf, 0402 180 pf 50 v sm0402 vj0402a181jxacw1bc vishay 1r30 res. 78.7 k ?? 1/10 w, 1 %, 0603 smd 78.7k 50 v sm0603 crcw060378k7fkea vishay 4 c7, c11, c14, c28 cap. 0.1 f, 50 v, 0603 0.1 f 50 v sm0603 vj0603y104kxacw1bc vishay 1 c5 cap. 0.1 f, 10 v, 0402 0.1 f 10 v sm0402 vj0402y104mxqcw1bc vishay 4 b1, b2, b3, b4 solder banana 575-6 keystone 1 c13 cap. 0.01 f, 50 v, 0402 0.01 f 50 v sm0402 vj0402y103kxacw1bc vishay 12 p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12 probe hook terminal 0 keystone 4 m1, m2, m3, m4 nylon on stand off 8834 keystone
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 19 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com pcb layout of the evaluation board figure 14. top layer figure 16. mid layer2 figure 15. mid layer1 figure 17. bottom layer
www.vishay.com 20 document number: 63388 s13-0248-rev. b, 04-feb-13 vishay siliconix sic414, sic424 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com package dimensions and marking info dimensions millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.175 0.225 0.275 0.007 0.009 0.011 d 4.00 bsc 0.157 bsc e 0.45 bsc 0.018 bsc e 4.00 bsc 0.157 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 n (3) 28 28 nd (3) 77 ne (3) 77 d2-1 0.912 1.062 1.162 0.036 0.042 0.046 d2-2 0.908 1.058 1.158 0.036 0.042 0.046 d2-3 0.908 1.058 1.158 0.036 0.042 0.046 e2-1 2.43 2.58 2.68 0.096 0.102 0.105 e2-2 1.30 1.45 1.55 0.051 0.057 0.061 e2-3 0.58 0.73 0.83 0.023 0.029 0.033 k1 0.46 bsc 0.018 bsc k2 0.40 bsc 0.016 bsc 6 5 2x a 2x b 4 c bottom view side view marking pin 1 dot by top view 1 2 3 28l t/slp (4.0 mm x 4.0 mm) 0.2030 ref. 0.000-0.0500 a e d (nd-1)x e ref. b e e2-1 d2-3 d2-1 d2-2 e2-2 e2-3 k1 l (ne-1)x e ref. 0.10 c b 0.10 c a 0.10 c a b 0.08 c k2 0.4000 pin 1 identification notes: 1. use millimeters as the primary measurement. 2. dimensioning and tolerances conform to asme y14.5m. - 1994. 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction. 4. dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 5. the pin #1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. 6. exact shape and size of this feature is optional. 7. package warpage max. 0.08 mm. 8. applied only for terminals.
vishay siliconix sic414, sic424 document number: 63388 s13-0248-rev. b, 04-feb-13 www.vishay.com 21 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com recommended land pattern notes: a. controlling dimensions are in millimeters (angles in degrees). b. this land pattern is for reference purposes only. consult y our manufacturing group to ensure your company?s manufacturing gui delines are met. c. square package-dimensions apply in both x and y directions. vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63388 . 2.5 8 x k p 1.29 k g h1 h2 1.29 h y (c) z dimensions millimeters c (3.95) g 3.20 h 2.58 h1 0.73 h2 1.45 k 1.06 p 0.45 x 0.30 y 0.75 z 4.70
document number: 65739 www.vishay.com revision: 22-feb-10 1 package information vishay siliconix powerpak ? mlp44-28l case outline dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref 0.008 ref b (4) 0.175 0.225 0.275 0.007 0.009 0.011 d 4.00 bsc 0.157 bsc e 0.45 bsc 0.018 bsc e 4.00 bsc 0.157 bsc l 0.30 0.40 0.50 0.012 0.016 0.020 n (3) 28 28 nd (3) 77 ne (3) 77 d2-1 0.908 1.058 1.158 0.036 0.042 0.046 d2-2 0.908 1.058 1.158 0.036 0.042 0.046 d2-3 0.912 1.062 1.162 0.036 0.042 0.046 e2-1 2.43 2.58 2.68 0.096 0.102 0.105 e2-2 1.30 1.45 1.55 0.051 0.057 0.061 e2-3 0.58 0.73 0.83 0.023 0.029 0.033 k1 0.46 bsc 0.018 bsc k2 0.40 bsc 0.016 bsc ecn: t10-0056-rev. a, 22-feb-10 dwg: 5996 6 5 2x a 2x b 4 c bottom view s ide view marking pin 1 dot by top view 1 2 3 28l t/ s lp (4.0 mm x 4.0 mm) 0.2030 ref. 0.000-0.0500 a e d (nd-1)x e ref. b e e2-1 d2-3 d2-1 d2-2 e2-2 e2-3 k1 l (ne-1)x e ref. 0.10 c b 0.10 c a 0.10 c a b 0.08 c k2 0.4000 pin#1 identification r0.20 note s : 1. u s e millimeter s a s the primary mea s urement. 2. dimen s ioning and tolerance s conform to a s me y14.5m. - 1994. 3. n i s the number of terminal s . nd i s the number of terminal s in x-direction and ne i s the number of terminal s in y-direction. 4. dimen s ion s b applie s to plated terminal and i s mea s ured between 0.15 mm and 0.30 mm from terminal tip. 5. the pin #1 identifier mu s t be exi s ted on the top s urface of the package by u s ing identification mark or other feature of package body. 6. exact s hape and s ize of thi s feature i s optional. 7. package warpage max. 0.08 mm. 8. applied only for terminal s .
document number: 70567 www.vishay.com revision: 17-may-10 1 pad pattern vishay siliconix powerpak ? mlp44-28l land pattern recommended land pattern recommended land pattern vs. case outline 0.30 0.06 0.06 0.06 1 2 3 0.75 0.400 2.58 1.06 0.45 2 3 1 0.30 1.29 1.06 3.95 1.45 0.73 0.75 1.29 2.58 3.20 4.70
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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